The present invention relates to an apparatus for demodulating frequency-modulated optical communication signals and magnetoelectric signals.
Of the digital data recording technics known heretofore, an NRZ (non-return-to-zero) system has been in practical application for a long time. In this system, however, there exist some disadvantages including a considerable variation that may occur in a recording frequency depending on the pattern of data to be recorded, the necessity of a timing signal for demodulation of the data in addition to the desired data signal to be recorded, and strict requirements relative to temporal phase deviation (skew) between the data signal and the timing signal. Under such circumstances, and FM system adapted to achieve improved digital data recording is widely employed today for the purpose of eliminating the disadvantages mentioned aove.
The FM system, which belongs to the category of self-clocking modulation techniques, is advantageous in comparison with the foregoing NRZ system since there never arises a problem with regard to skew and so forth due to the feature thereof that the data is transmitted in the form of a composite signal obtained by mixing the data and a timing signal (which is a clock pulse) with another signal. In demodulating the FM signal, however, when any large variation exists in the bit period of the signal, it is impossible to attain accurate demodulation. In an attempt to eliminate such defects, some improvements have been previously proposed as disclosed in the U.S. Pat. Nos. 3,902,129, 3,949,313 and 3,962,726.
An explanation will be given first with reference to the conventional demodulation system of FIG. 2 and the circuit diagram of FIG. 3 associated therewith. Supposing now that digital data "0011010001" is frequently modulated, its waveform becomes such as shown in FIG. 1. In the FM system, the signal level changes at each boundary of bit frames as illustrated, and when the data bit is "1", a level change further occurs at the intermediate point of each bit frame as well. Consequently, the recording frequency in the case of a bit "1" becomes double that of a bit "0", as shown in FIG. 1. The waveform of FIG. 1 is fed to an input circuit 11 of FIG. 3 to generate pulse trains (a), (b) and (c) shown in FIG. 2. As illustrated, the three pulse trains mutually have a slight timing difference and are composed of data-representing pulses (timing signals) and clock pulses mixed with each other. In FIG. 3, an oscillator 51 serves to generate a succession of pulses having a predetermined period. Labeled as 56 and 57 are frequency dividers. The pulse output of the frequency divider 56 is, for example, one third of the pulse input in number and has a duty cycle of 50 percent; while the pulse output of the frequency divider 57 is one fourth of the pulse input in number. Supposing now that a counter 54 and the frequency dividers 56 and 57 are cleared by the pulse train (b') in the preceding bit frame and the oscillator 51 produces 120 pulses during the present bit frame, then the content of the counter 54 becomes 30 (=120.times.1/4) at the termination of said bit frame. And the numerical value 30 thus obtained is loaded in an up-down counter 53 at the timing (a') of the next bit frame. The content of the up-down counter 53 is subtracted one by one in response to the output of the frequency divider 56 during the related bit frame. Since the output rate of the frequency divider 56 is 1/3, it follows that 40 pulses are obtained therefrom per bit frame, and therefore when the 31st pulse is produced from the divider 56, the counter 53 generates a borrow signal which is utilized as a clock output. Generation of such a borrow signal is effected at a time point of 31/40.apprxeq.3/4 in the bit frame. In FIG. 3, a gate control circuit 55 produces an output signal of (f) (see FIG. 2), and a demodulated-data output circuit 14 consists of a flip-flop. The pulse signal (f) and the input signal (a) are fed to an AND gate 18a, while the pulse signal (f) and the input signal (b) are fed to an AND gate 18b. Subsequently, the outputs of the two AND gates are fed as a set input (S) and a reset input (R) respectively to the flip-flop 14 to provide a data signal of (g) (see FIG. 2) in which the signals (a) and (b) are masked with the pulse signal (f). It is further possible to operate the up-down counter 53 in a count-up mode as well. In such a case, the complement of the output of the counter 54 is loaded in the counter 53 and, in place of the aforementioned borrow output, a carry output is used as a clock output.
In the conventional demodulator circuitry described above, it is necessary to provide, as a timing signal required for counting, timing pulses of 1/4 and 1/3 frequencies from the oscillator 51. Therefore, the output frequency of the oscillator 51 needs to be at least four times as high as the frequency of the timing pulses employed. This signifies a great burden in manufacture when assembling the said components in the form of an integrated circuit. Furthermore, in the latest technology with regard to magnetic recording and optical communication, a higher speed is required for processing FM signals through demodulation thereof within a shorter duration of a unit bit frame. And in order to meet such requirements, it naturally becomes necessary to furnish an oscillator of a higher frequency. In the foregoing example where the frequency is altered to 31/40.apprxeq.3/4 by utilizing the borrow or carry signal obtained from the counter 53, when the bit interval is short, there arises a problem that the error amounts to a large proportion and eventually induces an impediment to proper demodulation. In addition, the conventional apparatus sometimes causes incorrect demodulation of continuous FM signals due to bit-interval jitter in the bit frames or disturbance from external noise, which brings about another problem that the demodulation of all the successive FM signals posterior thereto are rendered incorrect.